1. Field of the Invention
The present invention relates to a communication system having a communication interface, such as High Definition Multimedia Interface (HDMI), capable of transmitting, for example, pixel data of non-compressed images in one direction, to an electronic apparatus therefor, and to a receiving method therefor.
2. Description of the Related Art
The specification “High-Definition Multimedia Interface Specification Version 1.3a” of HDMI has been distributed from HDMI LLC. In the standard of HDMI, a transmitter device is referred to as a source device, and a receiver device is referred to as a sink device.
The HDMI source and the HDMI sink have an HDMI connector to which an HDMI cable including a plurality of signal lines is connected. The HDMI connector is a connector for transmitting image data and audio data by using digital signals.
In the specification of HDMI, regarding HDMI, Transition Minimized Differential Signaling (TMDS) for transmitting pixel data and audio data at high speed from the HDMI source to the HDMI sink, and a Consumer Electronics Control (CEC) line for performing bidirectional communication between the HDMI source and the HDMI sink in one direction are defined, among others.
As described above, TMDS is used to transmit video/audio multiplexed signals of a wide band in HDMI, and is formed of one pair of differential pixel clocks and three pairs of differential serial data.
The three pairs of serial data signals are signals whose synchronization is achieved by a voltage controlled oscillator (VCO) clock generated by a common phase locked loop (PLL) in a transmitter. Therefore, although the three pairs of serial data have a phase difference due to a difference in the delay time of transmission lines, the mutual phase relationship is substantially fixed, and the basic frequency and jitter components match well.
However, only the pixel clock is not synchronized with a VCO clock of a PLL, and a reference clock that is input to the PLL is often output directly.
Therefore, the pixel clock has jitter components differing from serial data, and the clock and the phase of data constantly fluctuate dynamically.
In a receiver that receives such a group of signals and that correctly reproduces each of serial data signals, a phase-shift circuit is often used that adjusts the phase of a clock generated by a PLL frequency multiply circuit by using a pixel clock as a reference clock (see, for example, FUJITSU. 53.1, p. 47-53 (01, 2002). This method is called clock data recovery (CDR).
FIG. 1 shows, in a block diagram, a circuit disclosed in FUJITSU. 53.1, p. 47-53 (01, 2002).
A circuit 1 of FIG. 1 includes a PLL 2, clock phase shifters 3-0, 3-1, and 3-2, samplers 4-0, 4-1, and 4-2, and digital filters 5-0, 5-1, and 5-2.
An input pixel clock signal IPCK is multiplied by a PLL 2 including a phase-shift frequency detector (PFD) 21, a low-pass filter (LPF) 22, a VCO 23, and a frequency divider 24, and becomes a VCO clock VCK.
The VCO clock VCK may be a single phase clock or may be a set of multi-phase clocks in which specific phase differences are maintained.
The VCO clock VCK has a frequency equal to the bit rate of a serial data signal. However, the VCO clock VCK has jitter components possessed by the input pixel clock signal IPCK and jitter determined by the jitter characteristics of the PLL 2, which differ from the jitter possessed by the serial data signal.
Therefore, the phase difference between the VCO clock VCK and the serial data signal constantly fluctuates. If the VCO clock VCK is directly provided the samplers 4-0 to 4-2, it is not possible for the samplers to stably receive correct data.
Therefore, the clock phase shifters 3-0 to 3-2 are provided between the VCO 23 and the samplers 4-0 to 4-2, so that phase-shift clocks SCK0, SCK1, and SCK2 at which the samplers 4-0 to 4-2 can stably receive serial data are generated.
The amounts of changes in the phase of the clock phase shifters 3-0 to 3-2 are variable at several levels. The amounts of changes are determined by feedback control obtained by performing a filter operation, mainly, an integration operation, on information on the phase relationship between the phase-shift clock SCK detected by the samplers 4-0 to 4-2 and serial data.
A scheme for obtaining information on the phase relationship between the phase-shift clock and the serial data is disclosed in Japanese Patent No. 3239543.